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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Down
Figure 68: Power-Down Entry and Exit Timing
2 tCK (MIN)
CK/CK#
tIHCKE
Input clock frequency can be changed
or the input clock can be stopped during power-down. 1
tIHCKE
tCKE (MIN)
CKE
CS#
tISCKE
tCKE (MIN)
tISCKE
tXP (MIN)
Valid Enter NOP
CMD
PD
Exit
PD
NOP Valid Valid
Enter power-down mode
Exit power-down mode
Don’t Care
Note:
1. Input clock frequency can be changed or the input clock stopped during power-down,
provided that the clock frequency is between the minimum and maximum specified fre-
quencies for the speed grade in use, and that prior to power-down exit, a minimum of
two stable clocks complete.
Figure 69: CKE Intensive Environment
CK#
CK
t CKE
t CKE
t CKE
t CKE
CKE
Figure 70: REFRESH-to-REFRESH Timing in CKE Intensive Environments
CK#
CK
t CKE
t CKE
t CKE
t CKE
CKE
CMD
t XP
REFRESH
t REFI
t XP
REFRESH
Note:
1. The pattern shown can repeat over an extended period of time. With this pattern, all
AC and DC timing and voltage specifications with temperature and voltage drift are en-
sured.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
95
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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